Squaring the FIFO in GasP

This paper presents a method for designing a special type of asynchronous circuits, called Gasp circuits, and illustrates the method by a novel design of a low-latency, high-throughput FIFO, called a Square FIFO. The design method includes a graphical notation that permits the specification not only of circuit topology but also of the time separation between any two succeeding events. A Square FIFO test chip has been fabricated in a 0.35~ CMOS process through MOSIS. Test results show that the Square FIFO chip can sustain a maximum throughput of 1.56 Giga Data Items per second f o r a large range of occupancies.